Generally, an LSI test is performed by using automatic test equipment (ATE). Test data used in the ATE is generated by using the ATPG tool which can automatically generate a test pattern satisfying a remarkably high coverage (failure detection) in a short time. The test pattern generated by this ATPG tool (hereinafter, referred to as ATPG pattern) is used to verify system operation and timing, and is converted to a pattern to be interfaced to the ATE.
FIG. 1 is a flowchart which shows an outline of a conventional timing verification method for LSI test data. As shown in FIG. 1, conventionally, test synthesis is first performed based on a first netlist 121 (chip data 1) according to a specification based on customer requests or the like (step S121). Layout processing such as a cell arrangement and intercell wiring are performed based on a resultant second netlist 122 (chip data 2) (step S122).
The ATPG tool automatically generates an ATPG pattern based on a resultant third netlist 123 (chip data 3) (step S123). Data (test vector) 124 comprising the generated ATPG pattern is used to perform a timing verification with a gate simulation (step S124). This timing verification is started at the stage when verification of the system operation is almost completed. The verification of the system operation is omitted in FIG. 1.
When a violation is found as the result of the simulation, the first to third netlists 121, 122 and 123, and data (test vector) 124 are appropriately corrected (step S125). When the result of the gate simulation is good, the test vector is released to a production division (step S126), data (test vector) 125 comprising the test vector without violation is converted to an ATE data format (step S127). Thus, data (test vector) 126 comprising the ATE test vector is acquired. So far, the timing-verified test data is acquired. The acquired test data is used for an ATE test (step S128).
However, in recent years, a large scaling of an LSI has been advanced, and the data amount of the ATPG pattern has been remarkably increased. Therefore, there has been a problem that it takes an enormous time for the gate simulation. Further, when a timing failure is found with the simulation, the gate simulation is performed again after the failure is corrected, and therefore there has been a problem that it takes an enormous time to acquire verified test data. Further, there has been a problem that the data amount of the ATPG pattern is large and therefore a design environment such as a disk capacity to be used is pressed when the ATPG pattern is converted to the ATE pattern after the timing verification, or that it takes a very long time to handle the data.
As a measure against the problem that the gate simulation time is long, it is considered that the timing verification is performed on only a part of the ATPG patterns to reduce the verification time. However, with this, the timing verification is not performed on all the ATPG patterns, thereby, a yield in a shipment test may be greatly reduced.
When it is necessary to correct a critical portion (critical path) on the system operation as a result of the timing verification, a designer is burdened with finding the portion to be corrected from the ATPG patterns and manually performing a pattern correction.
Generally, with respect to the system operation, a static timing analysis tool (hereinafter, referred to as STA) is used to perform the timing verification for a synchronous circuit portion, and the gate simulation is performed only for an asynchronous circuit portion. Further, with respect to function verification, a formal verification tool is used to reduce the number of steps in the entire verification. As described above, in the other verification than the timing verification of the ATPG pattern, the verification time is reduced.
However, the STA is not used for the timing verification of the ATPG pattern. The reason is because, since a semiconductor designer does not know how to perform the timing verification of the test circuit automatically generated through test synthesis, a condition of the STA cannot be set. Further, the reason is because, since the result of performing the timing verification with the STA cannot be input into the ATPG tool and reflected, there is no assurance of a coincidence between the result of static timing analysis and the ATPG pattern. Further, when a test mode is erroneously set, a timing verification may be failed.
Further, as another reason why the STA is not used for the timing verification of the ATPG pattern, a high-speed simulator dedicated to a scan pattern may be considered. This high-speed simulator performs a reduction of a simulation time by omitting the timing verification with respect to a shift operation of the scan pattern. However, due to enlargement of LSI in recent years, it takes a very long time for the simulation even when this high-speed simulator is used.